A complex series of operations may be used to produce an integrated circuit (IC) package. One of those operations is to apply a protective layer to a wafer and form openings in the protective layer in the silicon foundry as a part of back end of line (BEOL) processing. This may involve utilizing a resist material as a mask to form the openings and then, after the openings are formed, removal of the resist material, which may be a costly process. In addition, because the passivation layer is opened at the foundry, metal contacts, or pads, exposed by the openings need to be made of a material that does not readily oxidize. Furthermore, because the openings in the passivation layer may be formed prior to disposition of a dielectric layer, vias formed in the dielectric layer will not fully align with the openings in the passivation layer.
The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.